1. Field of the Invention
The present invention generally relates to circuit performance detection systems, and more particularly to a network accuracy parasitic extraction system for determining the accuracy and sensitivity requirements for circuit networks.
2. Description of the Related Art
Parasitic extraction programs calculate the capacitances, resistances, and inductances (RLC) for all conductors connecting the circuit elements and add devices, which exist in the circuit layout and those which are not part of the designed circuitry. While this parasitic RLC information can have a small impact on the circuit performance it can very quickly add to the number of elements being analyzed or simulated and can have a significant impact on the simulation net list size, memory, and performance.
These parasitic extracted networks (parasitic resistance connected nodes) fall into at least three categories: networks that have insignificant or negligible capacitance and resistance when compared to the “designed circuitry”, networks that have small but relevant resistance and capacitance when compared to the “designed circuitry”, and networks whose parasitic contribution can be dominant.
When using a system to design microelectronic devices, a designer usually generates a behavioral description using a high-level description language or a circuit level description using a schematic capture tool. Then, the designer can incrementally simulate and verify the design using logic level models incorporating accurate timing and delay information. Here, the design is represented as logic cells having input and/or output ports. Furthermore, the circuit description includes structures called nets, which interconnect the ports on various logic cells and serve as the wiring connection for the circuit.
In every circuit the parasitic resistances and capacitances add to the non-parasitic resistances and capacitances which are part of the device model and are called out by the design schematic. The sum of the schematic and the parasitic resistance and capacitances impact circuit delay and other circuit performance parameters such as power, noise, skew, etc. Comparing a quick estimate of the expected parasitic values with the already existing schematic values allows the circuit designer to set the accuracy level and to decide whether the parasitic value is needed at all. In order to accomplish this, a system is needed to present the existing values to the extractor and to quickly estimate the expected values.
Conventional extraction programs simply ignore all elements smaller than a user-defined threshold. This passes the responsibility to do so to the user, and because the sensitivities to every net is different, the most sensitive net determines the threshold. Hence, these conventional processes are not efficient, and indeed involve a lot of wasted run time. Moreover, these conventional systems are also inaccurate as many small elements can add up to ignored values significantly larger than the threshold.
Furthermore, other conventional extraction processes apply RLC reduction routines after extraction. While this is more efficient than the programs described above, they increase the overall run-time and do not include circuit sensitivities. Still other conventional programs first run with a rough extraction, then run a timing estimate, and then determine where more accuracy is needed. While these methods serve a useful purpose, they require integration of the timing tool into the extraction tool, which unfortunately adds the additional run time of a “wasted” timing analysis.
Before the circuit layout is performed, the actual interconnect lengths between circuit elements remain unknown. As mentioned, estimates of parasitic resistance and capacitance may be used for logic delay calculations in the circuit. However, after the circuit layout is performed, the actual physical layout (length) of each net is identified, and a variety of improved approximations of interconnect resistance and capacitance (RC), obtained by parasitic RC extraction, may be employed in logic delay calculations.
As device and interconnect geometries decrease, the influence of interconnect impedance on total logic delay increases. Thus, the delay attributed to the interconnect impedance may rival or exceed the delay attributed to the transistor behavior of the driver cell and the effect of the load capacitances presented by load cells on the net. The impact of interconnect delay is so significant that a dominance of interconnect delay over gate delay in deep submicron IC technology is widely asserted in the field of electronic design. Accordingly, improvements in parasitic RC extraction can provide more accurate design simulations by improving overall logic delay accuracy. Thus, there remains a need for a new system and process to efficiently decide, in advance, the accuracy or sensitivity requirements for every network, and to increase the efficiency of a parasitic extraction program for networks.